EQ Circuit Idea

[raulduke]

Thanks for the explanation Madbean; that makes sense to me mate.

I have done a PCB design for this anyway (dual layer). Its a bit messy but its a start.

The tonestack values can always be altered to taste I guess.

I'll upload it as a .brd file if anyone is interested. I use gaussmarkov's libraries as well so they will need to be installed.

[oldhousescott]

I believe with JFETs, you only need the source resistor to set the bias, but it limits the input swing available as a large negative input will send the device into cutoff. Not necessarily a problem with guitar-level inputs.

[R.G.]

I believe the above is mostly correct. If R.G. Keen were here, I'm sure he could tell me how it's wrong .

You rang?

It doesn't need bias resistors on the gate -other than the pulldown resistor, which does pull the gate to the proper bias voltage of 0V - because it's biased at the source. Instead of pulling the control pin (gate for FET, base for bipolar, grid for tube...) to some predetermined voltage/current/whatever, source biasing pulls the source to a voltage/current/whatever to make the grid come out right.

In the self-biased circuit, which is what that is, the inherent current that flows through a depletion mode JFET is used to create a voltage through the source resistor that raises the source above ground. The gate is a very high impedance point, so it is easily held at ground by a single high value biasing resistor.

The source rising creates a voltage in the direction that turns the JFET off with the gate held at ground. The source rises until the net off-voltage between source and gate is just enough to hold the source where it is, and that condition is then stable. It's how triodes are most often biased, too, by the way.

1) JFETs have much lower current leakage from their gates than a bi-polar does from its base and

This is correct, although I would say it differently. Both JFETs and bipolars have very similar leakage from their control pins - that of a reverse-biased silicon junction. However, a bipolar is an enhancement-mode device. That means that left all to itself, it won't conduct at all. You have to do something to make it conduct. A bipolar MUST have a voltage forward biasing the base-emitter so current goes into the base to make it conduct.  JFETs are depletion-mode devices, meaning that left to itself it conducts maximum all the time. A JFETs with its gate open is a resistor between the drain and source of something like 10 to 1k ohms for most JFETs. You have to pull the gate negative with respect to the source (for N-channel; reverse for P-channel) to get it to back down towards off.

Which gets me to how I'd say it: JFETs bias differently from bipolars. Their gate has to be pulled negative with respect to the source. This circuit cleverly holds the gate at zero volts and the source pulls itself up to a stable bias voltage for the device. A bipolar has to have its base pulled higher than the emitter (analogous to source, kinda), hence external resistors are needed, because the default action of the bipolar won't obligingly self bias it.

2) the gate has a lower turn on voltage than the bipolar, hence the bias voltage is not needed to get the transistor to operate. Without the bias voltage, and because of the low leakage, a decoupling cap is not needed since current does not leak out into the input section of the circuit.

Again, correct, but I'd say it a little differently. In linear amplification operation, a JFET has a bigger magnitude gate-source voltage than a bipolar transistor's base-emitter voltage, but opposite polarity. An NPN bipolar base-emitter voltage is nearly always about 0.5 to 0.7V.  An N-channel JFET's gate-source voltage is always with the gate negative with respecto the the source, and usually within the range of 0.5V negative to maybe 8V negative. It depends hugely on the type number of the JFET and the specific JFET within the type number.

Which gets down to how I'd say it: The stable bias voltage for an N-channel JFET in the self bias circuit requires the gate to be held at ground while the source is elevated by the normal conduction of a depletion-mode JFET. Since the gate is very high impedance and does not either leak or suck current from any signal wire connected to it, an incoming signal which has an average DC level of zero volts does not need a DC-blocking capcitor to work properly with a self-biased JFET.

Notice that if the incoming signal does have an average DC level that's not zero, it will upset the self-bias balance of the JFET and so a blocking cap may be required to protect the JFET bias from the signal.

[madbean]

Thanks for the amazingly thorough and enlightening explanation! And, welcome to the forum!

[jkokura]

Heehee!

Welcome R.G.

For those of you around here who don't know, R.G. is a sort of 'grandfather' of DIY pedal building. He's a great, generous, helpful man who knows way more about this stuff than anyone else I know. He's also the guy who taught me about debugging.

R.G. - hope you're well, and it would be cool to see you around here once in a while.

Jacob

[nzCdog]

Hi RG, welcome to the forum!   Love your website www.geofex.com 

[k.rock!]

Ah! The legend himself! Welcome home RG haha hope you can hang out with us more often It's a real pleasure...

-Kaleb

[raulduke]

Welcome to the forum RG Keen!

And thanks for the thorough explanation!

[shawnee]

Ah! The legend himself! Welcome home RG haha hope you can hang out with us more often It's a real pleasure...

-Kaleb

Dido!!!

[raulduke]

Attached are the schematic file and board file for the baxandall eq schematic shown above.

I don't know if it will be of any use to anyone but I thought I would post it just in case someone wants to modify/change the design.

It is a dual layer board but could easily be made single layer with a bit of tweaking (and a larger board area).

R4 on the schematic can be changed to a pot (say 25K) to provide a 'shift' control for the mid frequency.




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[raulduke]

Doh!

brd and sch files attached here...

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