Current Lover clock buffer??

[Govmnt_Lacky]

Hoping someone smarter than I can answer this question 

On the Current Lover project, Brian uses a CD4049 as a "buffer" for the clock signal before being sent to the MN3007. So my question is....

Why is the CD4049 needed? Why can't the clock signals be directly sent to the MN3007 like they are for SAD1024?

I am probably even wrong calling it a "buffer" but that is why I am asking.

Thanks!! 

[Govmnt_Lacky]

Anyone??

Brian??

Bueller??

[Scruffie]

It overcomes the inherent clock capacitance of the 3007 to push the chip above its limits and in to shorter delay times than normally possible. The SAD has lower capacitance (plus isn't only half used? Can't recall).

(Said in monotone bueller teacher voice :p )

[Govmnt_Lacky]

It overcomes the inherent clock capacitance of the 3007 to push the chip above its limits and in to shorter delay times than normally possible. The SAD has lower capacitance (plus isn't only half used? Can't recall).

(Said in monotone bueller teacher voice :p )

Thanks for the explanation 

Could you elaborate a bit? What would happen if the direct clock signal was fed into the 3007?

Also, I believe in some flanger designs, the dual 512 stages were run in series. The MXR flanger comes to mind. The output of the first 512 stages was input to the second 512 stage. At least, I'm pretty sure that is how it is done   

[Scruffie]

It overcomes the inherent clock capacitance of the 3007 to push the chip above its limits and in to shorter delay times than normally possible. The SAD has lower capacitance (plus isn't only half used? Can't recall).

(Said in monotone bueller teacher voice :p )

Thanks for the explanation 

Could you elaborate a bit? What would happen if the direct clock signal was fed into the 3007?

Also, I believe in some flanger designs, the dual 512 stages were run in series. The MXR flanger comes to mind. The output of the first 512 stages was input to the second 512 stage. At least, I'm pretty sure that is how it is done   

In the MXR case you are correct, however with lower capacitance on the chip (110pF vs 700pF) it can still be pushed more than a normal 3007 by a standard clock.

Without the buffer, it would not sweep in to the lower more flangey delay times, the 3007 is speced for 5.12mS minimum delay, we want stuff more in the 0.5 - 1mS (depending on what it is) delay range for flange, so we overcome the barrier if you will by making the clock have extra push to get it down to those smaller bucket times and use clock frequencies it wasn't designed for.

The SAD is speced to 340uS minimum... even with both halves that's 680uS

It keeps the clock square wave square at the end of the day so the chip works normally.