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Show posts MenuQuote from: jessenator on July 09, 2024, 04:45:15 PMOne other thing that's been in my head is the DRC rules for whomever you're sending this to for fabrication. Should be easily found with an internet search.Yeah luckily I found them a while back. I've made a few boards years ago, but basically forgot just about everything I learned then. Good call on adjusting the pads as well. Much appreciated.
E.g. I searched for "eagle drc file jlcpcb" and got a 2-layer file that I've been using for a while now for things I send to JLC.
That'll help to make sure your files aren't kicked back because of incorrect spacing or borders—the ground plane and those two pads at the bottom look really close to the edge of the board boundaries, mainly.
Quote from: mauman on June 05, 2024, 03:07:45 AMAt Q1-Q4, signal goes into the gate, and should come out the drain amplified. If you have signal at the gate and not the drain, the FET is the location of the problem, if not the source of the problem.That was it. The docs were wrong about the way the transistors faced and it was printed incorrectly on the circuit board too. Put in sockets for all 4 after taking them out. Turned them around and everything worked. Thanks for the assist!
Some things I would check: What parts am I using for Q1-Q4? Are they known good FETs or could one or more be faulty? Do the pinouts match the PCB (D-G-S)?
Quote from: EBK on October 18, 2022, 03:32:51 PMI like using google notes or sheets for an extra level of backup for my notes. Free and will "always" be there. Plus. I lose stuff a ton lol.
For posterity (and in case I lose my notes):
I used 2N2222A transistors (different from the ones in the original gut shot). They measured:
Q1 = 96
Q2 = 145
Q3 = 210